| Embedded P1394A OHCI Link and PHY core function into a single host controller
1394 Link Core
32-bit CRC generator and checker for receive and transmit data
On-chip isochronous and asynchronous receive and transmit FIFOs for packets
Cycle master and isochronous resource manager capable
Supports P1394A accelerations features OHCI Compliant Programming Interface
Complies with 1394 OpenHCI Specifications V1.0 and V1.1
Compatible
with Microsoft OHCI, DV, and SBP-2 driver in Windows 98, Windows ME,
Windows 2000, Windows XP, and MacOS Operating System
Dedicated deep FIFOs for isochronous transmit, asynchronous transmit, isochronous receive, and asynchronous receive
Dedicated asynchronous and isochronous descriptor-based DMA engines
Multiple isochronous transmit and receive contexts
Supports posted write transaction
32-Bit Power-Managed PCI Bus Interface
Compliant with PCI specification 2.2
High Performance Bus Mastering Support
Programmable burst size for PCI data transfer
Compliant with PCI Bus Power Management Specification V1.1
Integrated 400Mbit PHY
Compliant with IEEE 1394-1995 Standard for High Performance Serial Bus and P1394A Supplement 4.0
Each 1394A fully compliant cable port supporting 100/200/400Mbps
24.576 crystal oscillator and PLL provide TX/RX data at 100/200/400Mbps and linker-Layer Controller clock at 49.152 Mhz
Cable power presence monitoring
Integrate 400Mbit PHY
Automatic
power down inactive circuit and logic for lower power application Fully
Support real time dynamic insertion and removal of devices |